

`define SRAM_48x512_DPRAM_DATA_WIDTH	48
`define SRAM_48x512_DPRAM_ADDR_WIDTH 	9
`timescale 1ns/1ps
module SRAM_48x512_DPRAM(
	ena,
	enb,
	clka, 
	addra, 
	dina, 
	douta, 
	clkb, 
	addrb, 
	dinb, 
	doutb,
	wea,
	web
);

// parameter SRAM_48x512_DPRAM_DATA_WIDTH = 48; 
// parameter SRAM_48x512_DPRAM_ADDR_WIDTH = 9; 

input clka;
input ena;
input enb;
input [`SRAM_48x512_DPRAM_ADDR_WIDTH-1:0]addra; 
input [`SRAM_48x512_DPRAM_DATA_WIDTH-1:0]dina; 
output [`SRAM_48x512_DPRAM_DATA_WIDTH-1:0]douta; 
input clkb; 
input [`SRAM_48x512_DPRAM_ADDR_WIDTH-1:0]addrb; 
input [`SRAM_48x512_DPRAM_DATA_WIDTH-1:0]dinb; 
output [`SRAM_48x512_DPRAM_DATA_WIDTH-1:0]doutb;
input wea;
input web;


//BIST Multiplexor
wire [`SRAM_48x512_DPRAM_ADDR_WIDTH-1:0] TAA;
wire [`SRAM_48x512_DPRAM_DATA_WIDTH-1:0] TDA;
wire  TENA;
wire  TCENA;
wire  TWENA;
wire  SEA;
wire [1:0] SIA;
wire  [`SRAM_48x512_DPRAM_ADDR_WIDTH-1:0] AYA;
wire   CENYA;
wire   WENYA;
wire  [1:0] SOA; // 11

wire [`SRAM_48x512_DPRAM_ADDR_WIDTH-1:0] TAB;
wire [`SRAM_48x512_DPRAM_DATA_WIDTH-1:0] TDB;
wire  TENB;
wire  TCENB;
wire  TWENB;
wire  SEB;
wire [1:0] SIB;
wire  [`SRAM_48x512_DPRAM_ADDR_WIDTH-1:0] AYB;
wire   CENYB;
wire   WENYB;
wire  [1:0] SOB; // 11

wire  RET1N;
wire  DFTRAMBYP;
wire  COLLDISN;	 // 3


assign TENA  = 1'b1;
assign TCENA = 1'b1;
assign TWENA = 1'b1;
assign SEA   = 1'b0;

assign TENB  = 1'b1;
assign SEB   = 1'b0;
assign TCENB = 1'b1;
assign TWENB = 1'b1;

assign DFTRAMBYP = 1'b0;
assign COLLDISN = 1'b1;
assign RET1N = 1'b1;

//Basic 
wire  CLKA;
wire  CENA;
wire  WENA;
wire [`SRAM_48x512_DPRAM_ADDR_WIDTH-1:0] AA;
wire [`SRAM_48x512_DPRAM_DATA_WIDTH-1:0] DA;
wire [2:0] EMAA;
wire [1:0] EMAWA;
wire  [`SRAM_48x512_DPRAM_DATA_WIDTH-1:0] QA; // 8

wire  CLKB;
wire  CENB;
wire  WENB;
wire [`SRAM_48x512_DPRAM_ADDR_WIDTH-1:0] AB;
wire [`SRAM_48x512_DPRAM_DATA_WIDTH-1:0] DB;
wire [2:0] EMAB;
wire [1:0] EMAWB;
wire  [`SRAM_48x512_DPRAM_DATA_WIDTH-1:0] QB; // 8

assign CLKA  = clka;
assign CLKB  = clkb;
assign #1 CENA  = ~ena;
assign #1 CENB  = ~enb;
assign #1 WENA  = ~wea;
assign #1 WENB  = ~web;
assign #1 AA    = addra;
assign #1 AB    = addrb;
assign #1 DA    = dina;
assign #1 DB    = dinb;
assign douta = QA;
assign doutb = QB;
assign EMAA  = 3'b010;
assign EMAB  = 3'b010;
assign EMAWA = 2'b00;
assign EMAWB = 2'b00;


// tie useless input IO to fixed state
assign TAA    = `SRAM_48x512_DPRAM_ADDR_WIDTH'd0;
assign TDA    = `SRAM_48x512_DPRAM_DATA_WIDTH'd0;
assign SIA    = 2'd0;

assign TAB    = `SRAM_48x512_DPRAM_ADDR_WIDTH'd0;
assign TDB    = `SRAM_48x512_DPRAM_DATA_WIDTH'd0;
assign SIB    = 2'd0;


// dpram1_1024 dpram1_1024_RAM1024x52 (CENYA, WENYA, AYA, CENYB, WENYB, AYB, QA, QB, SOA, SOB, CLKA, CENA, // 12
//     WENA, AA, DA, CLKB, CENB, WENB, AB, DB, EMAA, EMAWA, EMAB, EMAWB, TENA, TCENA, // 14
//     TWENA, TAA, TDA, TENB, TCENB, TWENB, TAB, TDB, RET1N, SIA, SEA, DFTRAMBYP, SIB, // 13
//     SEB, COLLDISN);  // 2

// dpram1_1024 dpram1_1024_RAM1024x52 (
// 	//Basic
// 	.CLKA(CLKA), .CENA(CENA), .WENA(WENA), .AA(AA), .DA(DA), .EMAA(EMAA), .EMAWA(EMAWA), .QA(QA), // 8
// 	.CLKB(CLKB), .CENB(CENB), .WENB(WENB), .AB(AB), .DB(DB), .EMAB(EMAB), .EMAWB(EMAWB), .QB(QB), // 8
// 	//BIST Multiplexor
// 	.TAA(TAA), .TDA(TDA), .TCENA(TCENA), .TENA(TENA), .TWENA(TWENA), .SEA(SEA), .SIA(SIA), .AYA(AYA), .CENYA(CENYA), .WENYA(WENYA), .SOA(SOA), // 11
// 	.TAB(TAB), .TDB(TDB), .TCENB(TCENB), .TENB(TENB), .TWENB(TWENB), .SEB(SEB), .SIB(SIB), .AYB(AYB), .CENYB(CENYB), .WENYB(WENYB), .SOB(SOB), // 11
// 	.DFTRAMBYP(DFTRAMBYP), 
// 	.RET1N(RET1N), 
// 	.COLLDISN(COLLDISN)
//     );



// module sram_dp_48_512 (CENYA, WENYA, AYA, CENYB, WENYB, AYB, QA, QB, SOA, SOB, CLKA,		// 11
//     CENA, WENA, AA, DA, CLKB, CENB, WENB, AB, DB, EMAA, EMAWA, EMAB, EMAWB, TENA, TCENA,	// 15
//     TWENA, TAA, TDA, TENB, TCENB, TWENB, TAB, TDB, RET1N, SIA, SEA, DFTRAMBYP, SIB,		// 13
//     SEB, COLLDISN);	// 2

sram_dp_48_512 sram_dp_48_512_u0 (
	//Basic
	.CLKA(CLKA), .CENA(CENA), .WENA(WENA), .AA(AA), .DA(DA), .EMAA(EMAA), .EMAWA(EMAWA), .QA(QA), // 8
	.CLKB(CLKB), .CENB(CENB), .WENB(WENB), .AB(AB), .DB(DB), .EMAB(EMAB), .EMAWB(EMAWB), .QB(QB), // 8
	//BIST Multiplexor
	.TAA(TAA), .TDA(TDA), .TCENA(TCENA), .TENA(TENA), .TWENA(TWENA), .SEA(SEA), .SIA(SIA), .AYA(AYA), .CENYA(CENYA), .WENYA(WENYA), .SOA(SOA), // 11
	.TAB(TAB), .TDB(TDB), .TCENB(TCENB), .TENB(TENB), .TWENB(TWENB), .SEB(SEB), .SIB(SIB), .AYB(AYB), .CENYB(CENYB), .WENYB(WENYB), .SOB(SOB), // 11
	.DFTRAMBYP(DFTRAMBYP), 
	.RET1N(RET1N), 
	.COLLDISN(COLLDISN)
    );




endmodule

	




